20261023-ups_mp25_clk_update-v2-1-398d348ea8fd@foss.st.com › 20261023-ups_mp25_clk_update-v2-5-398d348ea8fd@foss.st.com

⚠ checkpatch

total: 0 errors, 1 warnings, 351 lines checked (warnings) · raw

checkpatch
 in dir /home/sashing/patch/build (timeout 1200 secs)
 watching logfiles {}
 argv: [b'checkpatch']
 environment:
  BUILDBOT_BASEDIR=/home/sashing
  BUILDMASTER=localhost
  DEBIAN_FRONTEND=noninteractive
  HOME=/home/sashing
  HOSTNAME=sashing
  LC_CTYPE=C.UTF-8
  PATH=/opt/sashing/tasks:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/opt/venv/bin
  PWD=/home/sashing/patch/build
  WORKERNAME=local1
  container=podman
 using PTY: False
WARNING: 'HSI' may be misspelled - perhaps 'HIS'?
#14: 
Add the HSI KER, HSE KER and MSI KER clocks as new RCC input clocks and
        ^^^

total: 0 errors, 1 warnings, 351 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit 8b88eba6107b ("clk: stm32mp25: add clock for D3 peripherals allocation for Cortex-CM0") has style problems, please review.

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
program finished with exit code 3
elapsedTime=1.918325